Hynix

512Mb | HY5DU12422AT

DDR3 SDRAM :[Com.][Mod.] DDR2 SDRAM :[Com.][Mod.] DDR SDRAM :[Com.][Mod.]

DDR2 SDRAM | DDR SDRAM | SDR SDRAM : [Com.] [Mod.]

Mobile SDR | Mobile DDR | PSRAM | Super Low Power SRAM | Low Power Slow SRAM

Technical Data Sheet

Part Number	Rev.	Updated Date	Remark
HY5DU12422AT	0.4	2004-04-08
HY5DU12422AT_D	0.1	2004-04-08
HY5DU12422ATP	0.1	2004-04-08	Lead Free

Simulation Model

Part Number	Rev.	Updated Date
IBIS	0.2	2004-04-28
Verilog	0.0	2004-04-28
VHDL	0.1	2005-01-31

Description

The HY5DU12422A(L)T is a 536,870,912-bit CMOS Double DataRate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory densityand high bandwidth.

This Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of theclock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.

Features

VDD, VDDQ = 2.5V +/- 0.2V
All inputs and outputs are compatible with SSTL_2 interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ)
On chip DLL align DQ and DQS transition with CK transition
DM mask write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
Programmable /CAS latency 2 / 2.5 / 3 supported
Programmable burst length 2 / 4 / 8 with both sequential and interleave mode
Internal four bank operations with single pulsed /RAS
Auto refresh and self refresh supported
tRAS lock out function supported
8192 refresh cycles / 64ms
JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch
Full and Half strength driver option controlled by EMRS

Ordering Information

Part No.	CL2	CL2.5	CL3	Remark (CL-tRCD-tRP)	Package
HY5DU12422A(L)T-D4	-	-	200MHz	DDR400 (3-4-4)	400mil 66pin TSOP-II
HY5DU12422A(L)T-D43	-	-	200MHz	DDR400 (3-3-3)
HY5DU12422A(L)T-J	133MHz	166MHz	-	DDR333 (2.5-3-3)
HY5DU12422A(L)T-M	133MHz	133MHz	-	DDR266 (2-2-2)
HY5DU12422A(L)T-K	133MHz	133MHz	-	DDR266A (2-3-3)
HY5DU12422A(L)T-H	100MHz	133MHz	-	DDR266B (2.5-3-3)
HY5DU12422A(L)T-L	100MHz	125MHz	-	DDR200 (2-2-2)