Hynix

128Mb | HY5DU28422BT

DDR3 SDRAM :[Com.][Mod.] DDR2 SDRAM :[Com.][Mod.] DDR SDRAM :[Com.][Mod.]

DDR2 SDRAM | DDR SDRAM | SDR SDRAM : [Com.] [Mod.]

Mobile SDR | Mobile DDR | PSRAM | Super Low Power SRAM | Low Power Slow SRAM

Technical Data Sheet

Part Number	Rev.	Updated Date	Remark
HY5DU28422BT	0.3	2004-04-07

Simulation Model

Part Number	Rev.	Updated Date	Remark
IBIS	0.0	2004-04-28
Verilog	0.0	2004-04-28
VHDL	0.0	2004-04-28

Description

The Hynix HY5DU28422B(L)Tis a 134,217,728-bit CMOS Double Data Rate(DDR) Synchro-nous DRAM, ideally suited for the main memory applications which requires large memory density and high band-width. The Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock.
While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.
All input and output voltage levels are compatible with SSTL_2.

Features

IBIVDD, VDDQ = 2.5V +/- 0.2V
All inputs and outputs are compatible with SSTL_2 interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ)
On chip DLL align DQ and DQS transition with CK transition
DM mask write data-in at the both rising and falling edges of the data strobe
tRAS Lock-out function supported
All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
Programmable /CAS latency 2 and 2.5 supported
Programmable burst length 2 / 4 / 8 with both sequential and interleave mode
Internal four bank operations with single pulsed /RAS
Auto refresh and self refresh supported
4096 refresh cycles / 64ms
JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch
Full and Half strength driver option controlled by EMRS

Ordering Information

Part No.	CL2	CL2.5	Remark (CL-tRCD-tRP)	Package
HY5DU28422BT-J	133MHz	166MHz	DDR333 (2.5-3-3)	400mil 66pin TSOP-II
HY5DU28422BT-M	133MHz	133MHz	DDR266 (2-2-2)
HY5DU28422BT-K	133MHz	133MHz	DDR266A (2-3-3)
HY5DU28422BT-H	100MHz	133MHz	DDR266B (2.5-3-3)
HY5DU28422BT-L	100MHz	125MHz	DDR200 (2-2-2)