Hynix

256Mb | HY5DU56422DFP

DDR3 SDRAM :[Com.][Mod.] DDR2 SDRAM :[Com.][Mod.] DDR SDRAM :[Com.][Mod.]

DDR2 SDRAM | DDR SDRAM | SDR SDRAM : [Com.] [Mod.]

Mobile SDR | Mobile DDR | PSRAM | Super Low Power SRAM | Low Power Slow SRAM

Technical Data Sheet

Part Number	Rev.	Updated Date	Remark
HY5DU56422DFP	1.1	2006-04-13	Lead free

Description

The HY5DU56422D(L)FP is a 268,435,456-bit CMOS Double DataRate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.

This Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of theclock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.

The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.

All input and output voltage levels are compatiblewith SSTL_2.

Features

VDD, VDDQ = 2.5V ±0.2V for DDR200, 266, 333 VDD, VDDQ = 2.6V ±0.1V for DDR400
All inputs and outputs are compatible with SSTL_2 interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ)
On chip DLL align DQ and DQS transition with CK transition
DM mask write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
Programmable CAS latency 2/2.5 (DDR200, 266, 333) and 3 (DDR400) supported
Programmable burst length 2/4/8 with both sequen-tial and interleave mode
Internal four bank operations with single pulsed /RAS
Auto refresh and self refresh supported
tRAS lock out function supported
8192 refresh cycles / 64ms
60 Ball FBGA Package Type
Full and Half strength driver option controlled by EMRS
Lead free (*ROHS Compliant)

Ordering Information

Part No.	CL-tRCD-tRP	Clock Rate		Package
HY5DU56422D(L)FP-D43	DDR400B(3-3-3)	200MHz@CL3		60ball FBGA
HY5DU56422D(L)FP-J	DDR333(2.5-3-3)	133MHz@CL2	166MHz@CL2.5
HY5DU56422D(L)FP-K	DDR266A(2-3-3)	133MHz@CL2	133MHz@CL2.5
HY5DU56422D(L)FP-H	DDR266B(2.5-3-3)	100MHz@CL2	133MHz@CL2.5
HY5DU56422D(L)FP-L	DDR200(2-2-2)	100MHz@CL2