• VDD ,VDDQ =1.8 +/- 0.1V
  • All inputs and outputs are compatible with SSTL_18 interface
  • Fully differential clock inputs (CK, /CK) operation
  • Double data rate interface
  • Source synchronous-data transaction aligned to bidirectional data strobe (DQS, /DQS)
  • Differential Data Strobe (DQS, /DQS)
  • Data outputs on DQS, DQS edges when read (edged DQ)
  • Data inputs on DQS centers when write(centered DQ)
  • On chip DLL align DQ, DQS and /DQS transition with CK transition
  • DM mask write data-in at the both rising and falling edges of the data strobe
  • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
  • Programmable CAS latency 3, 4, 5 and 6 supported
  • Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
  • Programmable burst length 4 / 8 with both nibble sequential and interleave mode
  • Internal four bank operations with single pulsed RAS
  • Auto refresh and self refresh supported
  • tRAS lockout supported
  • 8K refresh cycles /64ms
  • JEDEC standard 60ball FBGA(x4/x8) & 84ball FBGA(x16)
  • Full strength driver option controlled by EMRS
  • On Die Termination supported
  • Off Chip Driver Impedance Adjustment supported
  • Read Data Strobe supported (x8 only)
  • Self-Refresh High Temperature Entry
  • Partial Array Self Refresh support

Technical Data Sheet

Technical Data Sheet Technical Data Sheet의 Part Number, Rev., Update Date, Remark를 나타낸 표 입니다.
Part Number Rev. Update Date Remark
HY5PS12821CFP 0.8 2007-10-04  

Simulation Model

Simulation Model Simulation Model의 Part Number, Rev., Update Date, Remark를 나타낸 표 입니다.
Part Number Rev. Update Date Remark
IBIS 0.3 2007-07-30  
HSpice 0.1 2007-05-18  


SpeedSpeed의 Part Number, Speed를 나타낸 표 입니다.
Part Number Speed
E3 400 3-3-3
C4 533 4-4-4
Y5 667 5-5-5
S5 800 5-5-5
S6 800 6-6-6