H5RS5223CFR
The SK Hynix H5RS5223 is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits.
The SK Hynix H5RS5223 is internally configured as a eight-bank DRAM.
The SK Hynix H5RS5223 uses a double data rate architecture to achieve high-speed opreration.
The double date rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single read or write access for the SK Hynix H5RS5223 consists of a 4n-bit wide, every two-clock-cycles data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the SK Hynix H5RS5223 is burst oriented; accesses start at a selected locations and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command, which is then followed by a READ of WRITE command.
The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0,BA1, BA2 select the bank; A0-A11 select the row).
The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
Prior to normal operation, the SK Hynix H5RS5223 must be initialized.

Features

Technical Data Sheet

Technical Data Sheet
Part Number Rev. Update Date Remark
H5RS5223CFR 1.5 2008-08-06  

Ordering Information