PRODUCTS

HY5RS123235FP

The SK Hynix HY5RS123235 is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits.  
The SK Hynix HY5RS123235 is internally configured as a eight-bank DRAM. 
The SK Hynix HY5RS123235 uses a double data rate architecture to achieve high-speed  opreration.
The double date rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single read or write access for the SK Hynix HY5RS123235 consists of a 4n-bit wide, every two-clock-cycles data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the SK Hynix HY5RS123235 is burst oriented; accesses start at a selected locations and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command, which is then followed by a READ of WRITE command.
The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0,BA1, BA2 select the bank; A0-A11 select the row).
The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
Prior to normal operation, the SK Hynix HY5RS123235 must be initialized.

Features

  • 2.2V +/-0.1V VDD/VDDQ power supply supports 900 / 800MHz
  • 2.0V VDD/ VDDQ wide range min/max power supply supports 700MHz
  • 1.8V VDD/ VDDQ wide range min/max power supply supports 500 / 600MHz
  • Single ended READ Strobe (RDQS) per byte
  • Single ended WRITE Strobe (WDQS) per byte
  • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
  • Calibrated output driver
  • Differential clock inputs (CK and CK#)
  • Commands entered on each positive CK edge
  • RDQS edge-aligned with data for READ; with WDQS center-aligned with data for WRITE
  • Eight internal banks for concurrent operation
  • Data mask (DM) for masking WRITE data
  • 4n prefetch
  • Programmable burst lengths: 4, 8
  • 32ms, 8K-cycle auto refresh
  • Auto precharge option
  • Auto Refresh and Self Refresh Modes
  • 1.8V Pseudo Open Drain I/O
  • Concurrent Auto Precharge support
  • tRAS lockout support, Active Termination support
  • Programmable Write latency(1, 2, 3, 4, 5, 6)
  • Boundary Scan Feature for connectivity test(refer to JEDEC std., not in this version of Specifications)

Technical Data Sheet

Technical Data Sheet Technical Data Sheet의 Part Number, Rev., Update Date, Remark를 나타낸 표 입니다.
Part Number Rev. Update Date Remark
HY5RS123235FP 1.5 2006-06-05  Lead free

Simulation Model

Simulation Model Simulation Model의 Part Number, Rev., Update Date, Remark를 나타낸 표 입니다.
Part Number Rev. Update Date Remark
IBIS 3.2 2005-07-20  
Hspice 0.1 2005-06-29  

Speed

SpeedSpeed의 Part Number, Speed를 나타낸 표 입니다.
Part Number Speed
11 900MHz
12 800MHz
14 700MHz
16 600MHz
2 500MHz