The SK Hynix HY5RS573225 is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits.
The SK Hynix HY5RS573225 is internally configured as a quad-bank DRAM.
The SK Hynix HY5RS573225 uses a double data rate architecture to achieve high-speed opreration.
The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single read or write access for the SK Hynix HY5RS573225 consists of a 4n-bit wide, every two-clock-cycles data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the SK Hynix HY5RS573225 is burst oriented; accesses start at a selected locations and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.
The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row).
The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
Prior to normal operation, the SK Hynix HY5RS573225 must be initialized.
- 2.2V +/- 0.1V VDD/ VDDQ power supply supports.(900/1000MHz)
- 1.8V VDD/ VDDQ wide range min/max power supply supports.
- 1.55V VDD/VDDQ wide range min/max power supply supports.
- Single ended READ Strobe (RDQS) per byte
- Single ended WRITE Strobe (WDQS) per byte
- Internal, pipelined double-data-rate (DDR) architec-ture; two data accesses per clock cycle
- Calibrated output drive
- Differential clock inputs (CK and CK#)
- Commands entered on each positive CK edge
- RDQS edge-aligned with data for READs; with WDQS center-aligned with data for WRITEs
- Four internal banks for concurrent operation
- Data mask (DM) for masking WRITE data
- 4n prefetch
- Programmable burst lengths: 4, 8
- 32ms, 4K-cycle auto refresh
- Auto precharge option
- Auto Refresh and Self Refresh Modes
- 1.8v Pseudo Open Drain I/O
- Concurrent Auto Precharge support
- tRAS lockout support, Active Termination support
- Programmable Write latency (1~7)
Technical Data Sheet
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