256Mb | HY5PS561621AFP
Technical Data Sheet
Features
- VDD/VDDQ=2.0V +/- 0.1V(500/450MHz)
- 1.8V VDD/VDDQ wide range max power supply supports(400/350/300MHz)
- All inputs and outputs are compatible with SSTL_18 interface
- Fully differential clock inputs (CK, /CK) operation
- Double data rate interface:two data transfers per clock cycle(tCK)
- Source synchronous-data transaction aligned to bidirectional data strobe (DQS, /DQS)
- Differential Data Strobe (DQS, /DQS)
- Data outputs on DQS, /DQS edges when read (edged DQ)
- Data inputs on DQS centers when write(centered DQ)
- On chip DLL align DQ, DQS and /DQS transition with CK transition
- DM mask write data-in at the both rising and falling edges of the data strobe
- All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
- Programmable CAS latency 4, 5, 6 and 7 supported
- Programmable additive latency 0, 1, 2, 3, 4, 5 supported
- Programmable burst length 4/8 with both nibble sequential and interleave mode
- Internal four bank operations with single pulsed RAS
- Auto refresh and self refresh supported
- tRAS lockout supported
- 8K refresh cycles /64ms
- JEDEC standard 84ball FBGA(x16)
- Full strength driver option controlled by EMRS
- On Die Termination supported
- Off Chip Driver Impedance Adjustment supported
- Partial Array Self Refresh supported
- High Temperature Self Refresh rate supported
Ordering Information
