PRODUCTS

HY27UF081G2A

The SK Hynix HY27UF(08/16)1G2A series is a 128Mx8bit with spare 4Mx8 bit capacity. The device is offered in 3.3V Vcc Power Supply.

Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The device contains 1024 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected Flash cells.

A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in typical 2ms on a 128K-byte(X8 device) block.

Data in the page can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of footprint. Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin. The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. The modify operations can be locked using the WP input pin or using the extended lock block feature described later. The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple memories the R/B pins can be connected all together to provide a global status signal.

Even the write-intensive systems can take advantage of the HY27UF(08/16)1G2A extended reliability of 100K program/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.

 

The chip could be offered with the CE don’t care function. This function allows the direct download of the code from the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation.

 

The copy back function allows the optimization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase.

The cache program feature allows the data insertion in the cache register while the data register is copied into the flash array. This pipelined program operation improves the program throughput when long files are written inside the memory. A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when consecutive pages have to be streamed out.

 

The SK Hynix HY27UF(08/16)1G2A series is available in 48 - TSOP1 12 x 20 mm, 48 - USOP 12 x 17 mm.

 

Features

  •  HIGH DENSITY NAND FLASH MEMORIES
    - Cost effective solutions for mass storage applications
  • NAND INTERFACE
    - x8 or x16 bus width.
    - Multiplexed Address/ Data
    - Pinout compatibility for all densities
  • SUPPLY VOLTAGE
    - VCC = 2.7 to 3.6V     : HY27UFXX1G2A
  • Memory Cell Array   
    = (2K+ 64) Bytes x 64 Pages x 1,024 Blocks   
    = (1K+32) Words x 64 pages x 1,024 Blocks
  • PAGE SIZE
    - x8 device  : (2K + 64 spare) Bytes                    
                      :  HY27UF081G2A
    - x16 device: (1K + 32 spare) Bytes
                      : HY27UF161G2A
  • BLOCK SIZE
    - x8 device:   (128K + 4K spare) Bytes
    - x16 device: (64K + 2K spare) Words
  • PAGE READ / PROGRAM
    - Random access: 25us (max.)
    - Sequential access: 30ns (min.)
    - Page program time: 200us (typ.)
  • COPY BACK PROGRAM MODE
    - Fast page copy without external buffering
  • CACHE PROGRAM MODE
    - Internal (2048+64)Byte buffer to improve the program throughput
  • FAST BLOCK ERASE
    - Block erase time: 2ms (Typ.)
  • STATUS REGISTER
  • ELECTRONIC SINGATURE
    - 1st cycle: Manufacture Code
    - 2nd cycle: Device Doce

    - 3rd cycle: Internal chip number, Cell Type, Number of Simultaneously Programmed 
    Pages.
    - 4th cycle: Page Size, Block Size, Oranization, Spare Size 

  • SERIAL NUMBER OPTION

  • CHIP ENABLE DON'T CARE OPTION
    - Simple interface with microcontroller
  • DATA INTEGRITY
    - 100,000 Program/Erase cycles (with 1bit/528byte ECC)
    - 10 years Data Retention
  • PACKAGE
    - HY27UF(08/16)1G2A-T(P)
    : 48-Pin TSOP1 (12 x 20 x 1.2 mm)              
    - HY27UF(08/16)1G2A-T (Lead)             
    - HY27UF(08/16)1G2A-TP (Lead Free)

    - HY27UF(08/16)1G2A-S(P)
    : 48-Pin USOP1 (12 x 17 x 0.65 mm)              
    - HY27UF(08/16)1G2A-S (Lead)             
    - HY27UF(08/16)1G2A-SP (Lead Free)

Technical Data Sheet

Technical Data Sheet Technical Data Sheet의 Part Number, Rev., Update Date, Remark를 나타낸 표 입니다.
Part Number Rev. Update Date Remark
HY27UF081G2A 0.4 2007-06-11