Hynix

Hynix (Relevance:32%)

... per clock cycle ? Mobile DDR SDRAM INTERFACE - x16 bus width: HY5MS7B6BLFP - Multiplexed Address (Row address and Column address) ? SUPPLY VOLTAGE - 1.8V device: VDD and VDDQ = 1.7V to 1.95V ? MEMORY CELL ARRAY - 512Mbit (x16 device) = 8M x 4Bank x 16 I/O ? DATA STROBE - x16 device: LDQS and UDQS ...
HY5PS124(8,16)21B(L)FP(Rev0.7).fm (Relevance:05%)

The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential strobe. Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc) min and the first crossing of ...
Hynix (Relevance:03%)

While all addresses and control inputs are latched on the rising edges of the CK (The Mobile DDR operates from a differential clock : the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it (Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK). All input and output voltage levels are ...