Hynix

Hynix (Relevance:72%)

... x32. The HYNIX HY5MS5B2ALFP series uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data per clock cycle at the I/O pins. The Hynix HY5MS5B2ALFP Series offers ...
Hynix (Relevance:27%)

While all addresses and control inputs are latched on the rising edges of the CK (The Mobile DDR operates from a differential clock : the crossing of CK going HIGH and /CK going LOW is referred to as the positive edge of CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it (Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK). Read and write accesses to the Low ...
Hynix (Relevance:00%)

While all addresses and control inputs are latched on the rising edges of the CK (The Mobile DDR operates from a differential clock : the crossing of CK going HIGH and /CK going LOW is referred to as the positive edge of CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it (Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK). Read and write accesses to the Low ...