DDR3 SDRAM

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H9TKNNN2GDMPLR

Features

[ PoP ]

  • Operation Temperature
    - -30oC ~ 85oC
  • Packcage
    - 168-ball FBGA
    - 12.0x12.0mm2, 0.8t, 0.5mm pitch
    - Lead & Halogen Free

[ LPDDR2 S4B ]

  • VDD1 = 1.8V (1.7V to 1.95V)
  • VDD2, VDDCA and VDDQ = 1.2V (1.14V to 1.30)
  • HSUL_12 interface (High Speed Unterminated Logic 1.2V)
  • Double data rate architecture for command, address and data Bus;
    - all control and address except CS_n, CKE latched at both rising and falling edge of the clock
    - CS_n, CKE latched at rising edge of the clock
    - two data accesses per clockcycle
  • Differential clock inputs (CK_t, CK_c)
  • Bi-directional differential data strobe (DQS_t, DQS_c)
    - Source synchronous data transaction aligned to bi-directional differential data strobe (DQS_t, DQS_c)
    - Data outputs aligned to the edge of the data strobe (DQS_t, DQS_c) when READ operation
    - Data inputs aligned to the center of the data strobe (DQS_t, DQS_c) when WRITE operation
  • DM masks write data at the both rising and falling edge of the data strobe
  • Programmable RL (Read Latency) and WL (Write Latency)
  • Programmable burst length: 4, 8 and 16
  • Auto refresh and self refresh supported
  • All bank auto refresh and per bank auto refresh supported
  • Auto TCSR (Temperature Compensated Self Refresh)
  • PASR (Partial Array Self Refresh) by Bank Mask and Segment Mask
  • DS (Drive Strength)
  • DPD (Deep Power Down)
  • ZQ (Calibration)

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